A phase-locked loop (PLL) is a negative feedback loop where an output phase of a voltage-controlled oscillator (VCO) can be automatically synchronized (“locked”) to a phase of a periodic input signal. The periodic input signal is commonly referred to as the input reference clock. The locking property of the PLL has numerous applications in communication systems such as frequency synthesis, frequency, amplitude, or phase modulation-demodulation, and clock and data recovery. A basic PLL has three components connected in a feedback loop: a VCO, a phase detector, and a loop filter, which is generally some type of low-pass filter. A basic PLL additionally includes a feedback frequency divider in applications where the VCO frequency is designed to be a multiple of a frequency of the input reference clock.
The VCO is an oscillator whose frequency is monotonically modulated by an input voltage. The voltage at the input of the VCO determines the frequency of a periodic signal at the output of the VCO. While the frequency of the VCO can be designed to decrease in response to an increase in the input voltage, VCO's are typically designed so as to increase frequency in response to an increasing input voltage. The only requirement is that when incorporated into the loop, a net polarity of the feedback must be negative.
The VCO output signal and the input reference clock are inputs to the phase detector. The phase detector produces an output voltage signal proportional to a phase difference between the input reference clock and the VCO output signal. The output of the phase detector is filtered by the low-pass loop filter. The loop is closed by connecting the loop filter output to the input of the VCO, such that the loop filter output voltage controls the frequency of the VCO. When the loop is “locked”, the phase and frequency of the VCO output are substantially equal to the phase and frequency of the input reference clock.
For monolithically integrated PLL's with low jitter requirements, such as those utilized in high-speed serial data transmission, both coarse and fine control of the VCO are typically desirable, as a single line control is generally not sufficient. Coarse control provides the tuning range necessary for the PLL to lock to its input reference clock amidst process, power supply voltage, and temperature (PVT) fluctuations; uncertainties in circuit modeling during the design process, and flexibility to adjust the input reference frequency for system test purposes. Fine control, with its smaller effect on the VCO output, allows the PLL to track small perturbations in input and voltage-temperature conditions during normal operation while providing high immunity against circuit noise that principally dictate jitter performance.
One conventional low jitter PLL configured as a frequency synthesizer employs a charge-pump loop filter providing the fine control voltage input to a varactor-tuned VCO, wherein the charge-pump loop filter is driven by a sequential phase-frequency detector (PFD). In one conventional implementation, the sequential PFD consists of two positive edge-triggered D (delay) latches and a logical AND-gate. The first latch senses rising edges in the input reference clock and the second latch rising edges in a feedback clock (i.e., VCO output divided by frequency divider) in respectively generating UP and DOWN outputs which serve as control inputs to the charge-pump loop filter. When both the UP and DOWN inputs are asserted HI, the AND-gate generates a RESET signal that clears both latch outputs concurrently, thereby resetting the sequential PFD for the next phase comparison.
The charge-pump loop filter traditionally consists of a pair of current sources that adjust the fine control voltage by adding or subtracting charge to a capacitor of a series connected RC load based on the states of the UP and DOWN inputs from the sequential PFD.
As is described in greater detail in the “Detailed Description” section below, a conventional PLL employing a charge-pump loop filter in this fashion inherently introduces jitter into the VCO output signal.